Altera cyclone V Technical Reference page 772

Hard processor system
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Creating a Qsys Project
• Create a Qsys project.
• Create a top-level file and add constraints.
• Create a Preloader BSP file.
• Create a Preloader image.
Creating a Qsys Project
Before you can generate a preloader image, you must create a Qsys project, as follows:
1. On the Tools menu in the software, click Qsys.
2. Under Component library, expand Embedded Processor System, select Hard Processor System and
click Add.
3. Specify parameters for the FPGA Interfaces, Peripheral Pin Multiplexing, and HPS Clocks, based on
your design requirements.
4. On the SDRAM tab, select the SDRAM protocol for your interface.
5. Populate the necessary parameter fields on the PHY Settings, Memory Parameters, Memory Timing,
and Board Settings tabs.
6. Add other Qsys components in your Qsys design and make the appropriate bus connections.
7. Save the Qsys project.
8. Click Generate on the Generation tab, to generate the Qsys design.
Creating a Top-Level File and Adding Constraints
This topic describes adding your Qsys system to your top-level design and adding constraints to your
design.
1. Add your Qsys system to your top-level design.
2. Add the IP files (
3. Perform analysis and synthesis on your design.
4. Constrain your EMIF design by running the
constraints script.
5. Add other necessary constraints—such as timing constraints, location assignments, and pin I/O
standard assignments—for your design.
6. Compile your design to generate an SRAM object file (
for creating a preloader image.
Note: You must regenerate the hardware handoff files whenever the HPS configuration changes; for
example, due to changes in Peripheral Pin Multiplexing or I/O standard for HPS pins.
Related Information
Altera SoC Embedded Design Suite User Guide
For more information on how to create a preloader BSP file and image.
Altera Corporation
) generated in step 2, to your project.
.qip
<variation_name>_p0_pin_assignments.tcl
) and the hardware handoff files necessary
.sof
cv_5v4
2016.10.28
pin
SDRAM Controller Subsystem
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