Altera cyclone V Technical Reference page 956

14-10
Interrupt Controller Unit
Bits
8 Response Timeout (RTO)/ Boot Ack Received
†
(BAR)
7 Data CRC Error (DCRC)
6 Response CRC Error (RCRC)
5 Receive FIFO Data Request (RXDR)
4 Transmit FIFO Data Request (TXDR)
Altera Corporation
Interrupt
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Description
• In Normal functioning mode: Response
timeout (RTO) Response timeout occurred.
Command Done (CD) also set if response
timeout occurs. If command involves data
transfer and when response times out, no
data transfer is attempted by SD/MMC
†
controller.
• In Boot Mode: Boot Ack Received (BAR)
When expect_boot_ack is set, on reception of
a boot acknowledge pattern—0-1-0—this
interrupt is asserted. A write to this register
with a value of 1 clears this interrupt.
Received Data CRC does not match with locally-
generated CRC in CIU; expected when a
negative CRC is received.
Response CRC does not match with locally-
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generated CRC in CIU.
Interrupt set during read operation from card
when FIFO level is greater than Receive-
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Threshold level.
Recommendation: In DMA modes, this
interrupt should not be enabled.
ISR, in non-DMA mode:
pop RX_WMark + 1 data from FIFO
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Interrupt set during write operation to card
when FIFO level reaches less than or equal to
Transmit-Threshold level.
Recommendation: In DMA modes, this
interrupt should not be enabled.
ISR in non-DMA mode:
if (pending_bytes > \
(FIFO_DEPTH - TX_WMark))
push (FIFO_DEPTH - \
TX_WMark) data into FIFO
†
else
push pending_bytes data \
†
into FIFO
2016.10.28
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SD/MMC Controller
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