Document Revision History - Altera cyclone V Technical Reference

1-20

Document Revision History

Slave Identifier
SPIM0
SPIM1
SCANMGR
ROM
MPU
MPUL2
OCRAM
Related Information
Cyclone V Address Map and Register Definitions
Web-based address map and register definitions
Document Revision History
Table 1-4: Document Revision History
Date
October 2016
May 2016
November 2015
May 2015
December 2014
July 2014
June 2014
February 2014
December 2013
November 2012
June 2012
Altera Corporation
Description
SPI master 0
SPI master 1
Scan manager registers
Boot ROM
MPU registers
MPU L2 cache controller
registers
On-chip RAM
Version
2016.10.28
• Added 8-bit support for eMMC for SD/MMC
• Renamed MPU Subsystem to Cortex-A9 MPCore
Maintenance release.
2016.05.03
2015.11.02 Updated the link to the Memory Maps.
2015.05.04 Corrected the base address for NANDDATA in the "Peripheral Region
Address Map" table.
2014.12.15 Maintenance release
2014.07.31 Updated address maps and register descriptions
2014.06.30 Maintenance release
2014.02.28 Maintenance release
2013.12.30 Maintenance release
1.3 Minor updates.
1.2 Updated address spaces section.
Base Address
0xFFF00000
0xFFF01000
0xFFF02000
0xFFFD0000
0xFFFEC000
0xFFFEF000
0xFFFF0000
Changes
Introduction to the Hard Processor System
2016.10.28
Size
4 KB
4 KB
4 KB
64 KB
8 KB
4 KB
64 KB
Send Feedback
cv_5v4