Altera cyclone V Technical Reference page 98

cv_5v4
2016.10.28
gpiodiv Fields
Bit
23:0
gpiodbclk
src
Contains fields that select the source clocks for the flash controllers. Fields are only reset by a cold reset.
Module Instance
clkmgr
Offset:
0xAC
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
src Fields
Bit
5:4
qspi
Clock Manager
Send Feedback
Name
The gpio_db_clk is divided down from the periph_
base_clk by the value plus one specified in this field.
The value 0 (divide by 1) is illegal. A value of 1
indicates divide by 2, 2 divide by 3, etc.
0xFFD04000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
Selects the source clock for the QSPI. Qsys and user
documenation refer to f2s_periph_ref_clk as f2h_
periph_ref_clk.
Value
0x0
0x1
0x2
Description
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Description
f2s_periph_ref_clk
main_qspi_clk
periph_qspi_clk
Access
Register Address
0xFFD040AC
21 20 19 18
5 4 3 2
qspi nand
RW 0x1 RW 0x1
Access
2-61
src
Reset
RW 0x1
17 16
1 0
sdmmc
RW 0x1
Reset
RW 0x1
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