Altera cyclone V Technical Reference page 262

5-68
bootstrap
bootstrap
Bootstrap fields sampled by NAND Flash Controller when released from reset. All fields are reset by a cold
or warm reset.
Module Instance
sysmgr
Offset:
0x110
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
bootstrap Fields
Bit
3
tworowaddr
2
noloadb0p0
1
page512
0
noinit
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
If 1, NAND device requires only 2 row address cycles
instead of the normal 3 row address cycles.
If 1, inhibits NAND Flash Controller from loading
page 0 of block 0 of the NAND device as part of the
initialization procedure.
If 1, NAND device has a 512 byte page size.
If 1, inhibits NAND Flash Controller from
performing initialization when coming out of reset.
Instead, software must program all registers
pertaining to device parameters like page size, width,
etc.
Base Address
0xFFD08000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Register Address
0xFFD08110
21 20 19 18
5 4 3 2
tworo noloa
waddr db0p0
RW RW
0x0 0x0
Access
cv_5v4
2016.10.28
17 16
1 0
page5 noinit
12
RW 0x0
RW
0x0
Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
System Manager
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