General Purpose I/O; Clock; Reset; Fpga Manager Address Map And Register Definitions - Altera cyclone V Technical Reference

cv_5v4
2016.10.28

General Purpose I/O

Thirty-two general purpose inputs and thirty-two general purpose outputs are provided to the FPGA and
are controlled through registers in the FPGA Manager.
No interrupts are generated through the input pins. All inputs are synchronized within the FPGA
Manager. Output signals should be synchronized in the FPGA.

Clock

The FPGA manager has two clock input signals which are asynchronous to each other. The clock manager
generates these two clocks:
•
cfg_clk
configuration. Enable this clock in the clock manager only when configuration is active or when the
configuration slave interface needs to respond to master requests.
•
l4_mp_clk
Related Information
Clock Manager

Reset

The FPGA manager has the
FPGA manager on a cold or warm reset. All distributed reset signals in the FPGA manager are asserted
asynchronously at the same time and deasserted synchronously to their associated clocks.
Related Information
Reset Manager

FPGA Manager Address Map and Register Definitions

The address map and register definitions for the FPGA Manager consist of the following regions:
• FPGA Manager Module
• FPGA Manager Module Configuration Data
Related Information
Introduction to the Hard Processor System

FPGA Manager Module Configuration Data Address Map

Registers in the FPGA Manager module accessible via its AXI slave
Base Address:
FPGA Manager Module Configuration Data
Register
data on page 4-10
FPGA Manager
Send Feedback
—the configuration slave interface clock input and also the
—the register slave interface clock.
on page 2-1
fpga_manager_rst_n
on page 3-1
0xFFB90000
Offset Width Acces
0x0
reset signal. The reset manager drives this signal to the
on page 1-1
Reset Value
s
32 RW 0x0
General Purpose I/O
output reference for FPGA
DCLK
Description
Write Data Register
Altera Corporation
4-9