Altera cyclone V Technical Reference page 781

cv_5v4
2016.10.28
Register
mppriority on page
11-72
remappriority
11-73
Port Sum of Weight Register
Register
mpweight_0_4
11-74
mpweight_1_4
11-75
mpweight_2_4
11-76
mpweight_3_4
11-76
SDRAM Controller Module Register Descriptions
Address map for the SDRAM controller and multi-port front-end. All registers in this group reset to zero.
Offset:
0x5000
ctrlcfg
on page 11-45
The Controller Configuration Register determines the behavior of the controller.
dramtiming1
This register implements JEDEC standardized timing parameters. It should be programmed in clock
cycles, for the value specified by the memory vendor.
dramtiming2
This register implements JEDEC standardized timing parameters. It should be programmed in clock
cycles, for the value specified by the memory vendor.
dramtiming3
This register implements JEDEC standardized timing parameters. It should be programmed in clock
cycles, for the value specified by the memory vendor.
dramtiming4
This register implements JEDEC standardized timing parameters. It should be programmed in clock
cycles, for the value specified by the memory vendor.
lowpwrtiming
This register controls the behavior of the low power logic in the controller.
SDRAM Controller Subsystem
Send Feedback
Offset Width Acces
0x50AC
on page 0x50E0
Offset Width Acces
on page 0x50B0
on page 0x50B4
on page 0x50B8
on page 0x50BC
on page 11-48
on page 11-49
on page 11-50
on page 11-50
on page 11-51
SDRAM Controller Module Register Descriptions
Reset Value
s
32 RW 0x0
32 RW 0x0
Reset Value
s
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
Description
Scheduler priority Register
Controller Command Pool
Priority Remap Register
Description
Port Sum of Weight Register[1/4]
Port Sum of Weight Register[2/4]
Port Sum of Weight Register[3/4]
Port Sum of Weight Register[4/4]
Altera Corporation
11-43