Altera cyclone V Technical Reference page 231

cv_5v4
2016.10.28
31 30
15 14
ctrl Fields
Bit
0
fpgajtagen
Freeze Control Group Register Descriptions
Registers used to generate HPS IO freeze signals. All registers are only reset by a cold reset (ignore warm
reset).
Offset:
0x40
vioctrl
on page 5-38
Used to drive freeze signals to HPS VIO banks. The register array index corresponds to the freeze channel.
Freeze channel 0 provides freeze signals to VIO bank 0 and 1. Freeze channel 1 provides freeze signals to
VIO bank 2 and 3. Only drives freeze signals when SRC.VIO1 is set to SW. Freeze channel 2 provides
freeze signals to VIO bank 4. All fields are only reset by a cold reset (ignore warm reset). The following
equation determines when the weak pullup resistor is enabled: enabled = ~wkpullup | (CFF & cfg &
tristate) where CFF is the value of weak pullup as set by IO configuration
hioctrl on page 5-39
Used to drive freeze signals to HPS HIO bank (DDR SDRAM). All fields are only reset by a cold reset
(ignore warm reset). The following equation determines when the weak pullup resistor is enabled: enabled
= ~wkpullup | (CFF & cfg & tristate) where CFF is the value of weak pullup as set by IO configuration
src on page 5-42
Contains register field to choose between software state machine (vioctrl array index [1] register) or
hardware state machine in the Freeze Controller as the freeze signal source for VIO channel 1. All fields
are only reset by a cold reset (ignore warm reset).
System Manager
Send Feedback
29 28 27 26
13 12 11 10
Name
Controls whether FPGA JTAG pins or Scan Manager
drives JTAG signals to the FPGA. Only reset by a cold
reset (ignores warm reset).
Value
0x0
0x1
Freeze Control Group Register Descriptions
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Description
FPGA JTAG pins drive JTAG signals to FPGA
Scan Manager drives JTAG signals to FPGA
21 20 19 18
5 4 3 2
Access
RW
5-37
17 16
1 0
fpgajtag
en
RW 0x0
Reset
0x0
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