Altera cyclone V Technical Reference page 140

cv_5v4
2016.10.28
brgmodrst
The BRGMODRST register is used by software to trigger module resets (individual module reset signals).
Software explicitly asserts and de-asserts module reset signals by writing bits in the appropriate *MODRST
register. It is up to software to ensure module reset signals are asserted for the appropriate length of time
and are de-asserted in the correct order. It is also up to software to not assert a module reset signal that
would prevent software from de-asserting the module reset signal. For example, software should not assert
the module reset to the CPU executing the software. Software writes a bit to 1 to assert the module reset
signal and to 0 to de-assert the module reset signal. All fields are reset by a cold reset.All fields are also
reset by a warm reset if not masked by the corresponding BRGWARMMASK field. The reset value of all
fields is 1. This holds the corresponding module in reset until software is ready to release the module from
reset by writing 0 to its field.
Module Instance
rstmgr
Offset:
0x1C
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
brgmodrst Fields
Bit
2
fpga2hps
1
lwhps2fpga
0
hps2fpga
miscmodrst
The MISCMODRST register is used by software to trigger module resets (individual module reset signals).
Software explicitly asserts and de-asserts module reset signals by writing bits in the appropriate *MODRST
register. It is up to software to ensure module reset signals are asserted for the appropriate length of time
Reset Manager
Send Feedback
0xFFD05000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
Resets FPGA2HPS Bridge
Resets LWHPS2FPGA Bridge
Resets HPS2FPGA Bridge
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
brgmodrst
Register Address
0xFFD0501C
21 20 19 18
5 4 3 2
fpga2
hps
RW
0x1
Access
3-29
17 16
1 0
lwhps hps2fpga
2fpga
RW 0x1
RW
0x1
Reset
RW 0x1
RW 0x1
RW 0x1
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