Altera cyclone V Technical Reference page 957

cv_5v4
2016.10.28
Bits
3 Data Transfer (DTO)
2 Command Done (CD)
1 Response Error (RE)
0 Card-Detect (CDT)
Interrupt Setting and Clearing
The SDIO Interrupts, Receive FIFO Data Request, and Transmit FIFO Data Request interrupts are set by
level-sensitive interrupt sources. Therefore, the interrupt source must be first cleared before you can reset
the interrupt's corresponding bit in the
SD/MMC Controller
Send Feedback
Interrupt
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rintsts
Interrupt Setting and Clearing
Data transfer completed, even if there is Start Bit
Error or CRC error. This bit is also set when
"read data-timeout" occurs or CCS is sampled
from CE-ATA device.
Recommendation: In non-DMA mode, when
data is read from card, on seeing interrupt, host
should read any pending data from FIFO. In
DMA mode, DMA controllers guarantee FIFO is
flushed before interrupt.
Note: DTO bit is set at the end of the last
data block, even if the device asserts
MMC busy after the last data block.
Command sent to card and received response
from card, even if Response Error or CRC error
occurs. Also set when response timeout occurs
or CCSD sent to CE-ATA device.
Error in received response set if one of following
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occurs:
• Transmission bit != 0
• Command index mismatch
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• End-bit != 1
When one or more cards inserted or removed,
this interrupt occurs. Software should read card-
detect register (CDETECT, 0x50) to determine
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current card status.
Recommendation: After power-on and before
enabling interrupts, software should read card
detect register and store it in memory. When
interrupt occurs, it should read card detect
register and compare it with value stored in
memory to determine which card(s) were
removed/inserted. Before exiting ISR, software
should update memory with new card-detect
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value.
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register to 0.
Description
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Altera Corporation
14-11