Clocks And Resets - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
IP Source and Destination Address should be programmed in the order defined in the IPv4 specification.
The specification requires that you program the first byte of received frame IP Source and Destination
Address in the higher byte of the respective register.
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The EMAC supports perfect matching or inverse matching for TCP or UDP Source and Destination Port
numbers. However, you can program only one type (TCP or UDP) at a time. The first data register
contains the 16-bit Source and Destination Port numbers of TCP or UDP, that is, the lower 16 bits for
Source Port number and higher 16 bits for Destination Port number.
The TCP or UDP Source and Destination Port numbers should be programmed in the order defined in the
TCP or UDP specification, that is, the first byte of TCP or UDP Source and Destination Port number in
the received frame is in the higher byte of the register.

Clocks and Resets

Clock Structure
The Ethernet Controller received five input clocks and generates one output clock.
The EMAC controller provides the clock division and muxing necessary to generate the proper clocks for
each of the PHY modes and data rates. The clock domains to the Ethernet controller are as follows
• l4_mp_clk clock
• EMAC RX clock
• EMAC TX clock
• clk_ptp_ref
Ethernet Media Access Controller
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