Resets - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
•
qspi_ref_clk
•
qspi_ref_clk
The
qspi_clk
( ) of the
bauddiv
Related Information
Clock Manager

Resets

A single reset signal (
manager drives the signal on a cold or warm reset.
Related Information
Reset Manager
Taking the Quad SPI Flash Controller Out of Reset
When a cold or warm reset is issued in the HPS, the reset manager resets this module and holds it in reset
until software releases it.
After the Cortex-A9 MPCore CPU boots, it can deassert the reset signal by clearing the appropriate bits in
the reset manager's corresponding reset register. For details about reset registers, refer to "Module Reset
Signals".
Interrupts
All interrupt sources are combined to create a single level-sensitive, active-high interrupt (
Software can determine the source of the interrupt by reading the interrupt status register (
default, the interrupt source is cleared when software writes a one (1) to the interrupt status register. The
interrupts are individually maskable through the interrupt mask register (
interrupt sources in the
Table 15-4: Interrupt Sources in the irqstat Register
Underflow detected
Indirect operation complete
Indirect read reject
Quad SPI Flash Controller
Send Feedback
should be greater than
must be greater than two times
clock is derived by dividing down the
register.
cfg
on page 2-1
qspi_flash_rst_n
on page 3-1
register.
irqstat
Interrupt Source
l4_mp_clk
qspi_clk
qspi_ref_clk
) is provided as an input to the quad SPI controller. The reset
When 0, no underflow has been detected. When 1,
the data slave write data is being supplied too slowly.
This situation can occur when data slave write data
is being supplied too slowly to keep up with the
requested write operation This bit is reset only by a
system reset and cleared only when a 1 is written to
it.
The controller has completed a triggered indirect
operation.
An indirect operation was requested but could not
be accepted because two indirect operations are
already in the queue.
Resets
clock by the baud rate divisor field
qspi_intr
irqstat
Table 15-4
).
irqmask
Description
Altera Corporation
15-13
).
). By
lists the