Altera cyclone V Technical Reference page 165

4-22
Configuration Monitor (MON) Registers Register Descriptions
Offset:
0x18
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
misci Fields
Bit
1
bootFPGArdy
0
bootFPGAfail
Configuration Monitor (MON) Registers Register Descriptions
The Configuration Monitor allows software to poll or be interrupted by changes in the FPGA state. The
Configuration Monitor is an instantiation of a Synopsys GPIO.
Only registers relevant to the MON operation are shown. The GPIO inputs are connected to the following
signals:
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
The value of the f2h_boot_from_fpga_ready signal
from the FPGA fabric. If the FPGA is not in User
Mode, the value of this field is undefined. 1 = FPGA
fabric is ready to accept AXI master requests from the
HPS2FPGA bridge. 0 = FPGA fabric is not ready
(probably still processing a reset).
The value of the f2h_boot_from_fpga_on_failure
signal from the FPGA fabric. If the FPGA is not in
User Mode, the value of this field is undefined. 1 =
Boot ROM will boot from FPGA if boot from normal
boot device fails. 0 = Boot ROM will not boot from
FPGA if boot from normal boot device fails.
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
21 20 19 18
5 4 3 2
Access
cv_5v4
2016.10.28
17 16
1 0
bootF bootFPGA
PGArd fail
y
RO 0x0
RO
0x0
Reset
RO 0x0
RO 0x0
FPGA Manager
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