Altera cyclone V Technical Reference page 588

8-6
FPGA-to-HPS Bridge Slave Signals
Signal
WDATA
WSTRB
WLAST
WVALID
WREADY
Table 8-5: FPGA-to-HPS Bridge Slave Write Response Channel Signals
Signal
BID
BRESP
BVALID
BREADY
Table 8-6: FPGA-to-HPS Bridge Slave Read Address Channel Signals
Signal
ARID
ARADDR
ARLEN
ARSIZE
ARBURST
ARLOCK
ARCACHE
ARPROT
ARVALID
ARREADY
Altera Corporation
Width Direction
32, 64, or 128 bits Input
4, 8, or 16 bits Input
1 bit Input
1 bit Input
1 bit Output
Width Direction
8 bits Output
2 bits Output
1 bit Output
1 bit Input
Width Direction
8 bits Input
32 bits Input
4 bits Input
3 bits Input
2 bits Input
2 bits Input
4 bits Input
3 bits Input
1 bit Input
1 bit Output
Description
Write data
Write data strobes
Write last data identifier
Write data channel valid
Write data channel ready
Description
Write response ID
Write response
Write response channel valid
Write response channel ready
Description
Read address ID
Read address
Burst length
Burst size
Burst type
Lock type—Valid values are 00 (normal access) and
01 (exclusive access)
Cache policy type
Protection type
Read address channel valid
Read address channel ready
cv_5v4
2016.10.28
HPS-FPGA Bridges
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