Altera cyclone V Technical Reference page 226

5-32
indiv
31 30
15 14
gbl Fields
Bit
0
intf
indiv
Used to disable individual interfaces between the FPGA and HPS.
Module Instance
sysmgr
Offset:
0x24
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Altera Corporation
29 28 27 26
13 12 11 10
Name
Used to disable all interfaces between the FPGA and
HPS. Software must ensure that all interfaces between
the FPGA and HPS are inactive before disabling
them.
Value
0x0
0x1
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Description
All interfaces between FPGA and HPS are
disabled.
Interfaces between FPGA and HPS are not all
disabled. Interfaces can be indivdually
disabled by putting the HPS module
associated with the interface in reset using
registers in the Reset Manager or by using
registers in this register group of the System
Manager for interfaces without an associated
module.
Base Address
0xFFD08000
21 20 19 18
5 4 3 2
Access
Register Address
0xFFD08024
cv_5v4
2016.10.28
17 16
1 0
intf
RW 0x1
Reset
RW 0x1
System Manager
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