Document Revision History - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
SPIM0USEFPGA
Selection between HPS Pins and FPGA Interface for SPIM0 signals. Only reset by a cold reset (ignores
warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for
dynamically changing the Pin Mux selections.
Module Instance
sysmgr
Offset:
0x738
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
SPIM0USEFPGA Fields
Bit
0
sel

Document Revision History

Table 5-4: Document Revision History
Date
October 2016
May 2016
November 2015
May 2015
December 2014
System Manager
Send Feedback
0xFFD08000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
Select connection for SPIM0. 0 : SPIM0 uses HPS
Pins. 1 : SPIM0 uses the FPGA Inteface.
Version
2016.10.28 Maintenance release.
2016.05.03 Maintenance release.
2015.11.02 Maintenance release.
2015.05.04 Maintenance release.
2014.12.15 Maintenance release.
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
SPIM0USEFPGA
Register Address
0xFFD08738
21 20 19 18
5 4 3 2
Access
Changes
5-237
17 16
1 0
sel
RW 0x0
Reset
RW 0x0
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