Altera cyclone V Technical Reference page 117

3-6
Module Reset Signals
The column marked for Software Deassert denotes reset signals that are left asserted by the reset manager.
Table 3-3: MPU Group, Generated Module Resets
Module Reset Signal
mpu_cpu_rst_n[0]
mpu_cpu_rst_n[1]
mpu_wd_rst_n
mpu_scu_periph_rst_n
mpu_l2_rst_n
Table 3-4: PER Group, Generated Module Resets
Module Reset Signal
emac_rst_n[1:0]
usb_rst_n[1:0]
nand_flash_rst_n
qspi_flash_rst_n
watchdog_rst_n[1:0]
osc1_timer_rst_n[1:0]
sp_timer_rst_n[1:0]
Altera Corporation
Description Reset
Domain
Resets each System
processor in the
MPU
Resets each System
processor in the
MPU
Resets both per- System
processor
watchdogs in the
MPU
Resets Snoop System
Control Unit
(SCU) and
peripherals
Level 2 (L2) System
cache reset
Description
Resets each EMAC
Resets each USB
Resets NAND flash
controller
Resets quad SPI flash
controller
Resets each system watchdog
timer
Resets each OSC1 timer
Resets each SP timer
Cold Warm Debug
Reset Reset Reset
X X
X X
X X
X X
X X
Reset Cold Warm
Domai Reset Reset
n
System X X
System X X
System X X
System X X
System X X
System X X
System X X
cv_5v4
2016.10.28
Software Deassert
X
Software
Debug
Deassert
Reset
X
X
X
X
X
X
X
Reset Manager
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