System Interconnect Resets - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Data Release Mechanism
For system interconnect ports with data FIFO buffers whose depth is greater than zero, you can set a write
tidemark function,
following situations occurs:
• The system interconnect receives the
• The write data FIFO buffer becomes full.
• The number of occupied slots in the write data FIFO buffer exceeds the write tidemark.
Related Information
• System Interconnect Master Properties
Indicates which master interfaces have data FIFO buffers with a nonzero depth
• Interconnect Slave Properties
Indicates which slave interfaces have data FIFO buffers with a nonzero depth

System Interconnect Resets

The system interconnect has one reset signal. The reset manager drives this signal to the system intercon‐
nect on a cold or warm reset.
Related Information
Reset Manager
System Interconnect Address Map and Register Definitions
This section lists the system interconnect register address map and describes the registers.
Note: System interconnect slaves are available for connection from peripheral masters. System intercon‐
nect masters connect to peripheral slaves. This terminology is the reverse of conventional
terminology used in Qsys.
Related Information
Introduction to the Hard Processor System
•
The base addresses of all modules are also listed in the Introduction to the Hard Processor chapter.
Cyclone V Address Map and Register Definitions
•
Web-based address map and register definitions
L3 (NIC-301) GPV Registers Address Map
Registers to control L3 interconnect settings
Base Address:
L3 (NIC-301) GPV Registers
Register
remap on page 7-32
System Interconnect
Send Feedback
. This tidemark level stalls the release of the transaction until one of the
wr_tidemark
on page 7-17
on page 3-1
0xFF800000
Offset Width Acces
0x0 32
beat of a burst.
WLAST
on page 7-16
on page 1-1
Reset Value
s
WO 0x0
Data Release Mechanism
Description
Remap
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7-23