Altera cyclone V Technical Reference page 701

cv_5v4
2016.10.28
The ECC protection bits are not valid in the following cases:
• Data is written that is not 64-bit aligned in memory
• Data is written that is less than 64 bits in width
In these cases the Byte Write Error interrupt is asserted. Cache data is still written when such an error
occurs. However, the ECC error detection and correction continues to function. Therefore, the cache data
is likely to be incorrect on subsequent reads.
To use ECCs, the software and system must meet the following requirements:
• L1 and L2 cache must be configured as write-back and write-allocate for any cacheable memory region
• Level 3 interconnect masters using the ACP must only perform the following types of data writes:
• 64-bit aligned in memory
• 64-bit wide accesses
Note that system interconnect masters can include masters in the FPGA accessing the FPGA-to-HPS
bridge.
If a correctable ECC error occurs, the ECC corrects the read data in parallel to asserting a correctable
error signal on the AXI bus. If an uncorrectable error occurs in the L2 cache, the uncorrected data remains
in the L2 cache and an AXI slave error (SLVERR) is sent to the L1 memory system. In addition, interrupts
can be enabled for correctable and uncorrectable ECC errors through the GIC.
Related Information
System Manager
For more information about SEU errors, refer to the System Manager chapter.
L2 Cache Parity
Because the L2 data RAM is ECC-protected, parity checking on the data RAM is not required. However,
because the tag RAM is not ECC protected, it requires parity checking. Because parity cannot be
configured independently, parity checking for both the data RAM and tag RAM must be enabled.
Ideally, parity should be enabled before the L2 cache is enabled. If the cache is already enabled, you must
clean the cache and disable it before parity is enabled. After enabling parity, the cache is invalidated and
enabled. To enable parity:
1. Set the
Parity_on
2. Invalidate the L2 cache through the
3. Enable the cache through the
Note: If you would like the parity errors to be reported you must enable the parity interrupts in the
Interrupt Mask
controller (GIC).
Refer to the ARM Infocenter website for more information regarding L2 cache registers and program‐
ming.
Parity Error Handling
If a parity error occurs in the tag or data RAM during AXI read transactions, a SLVERR response is
reported through the event bus and interrupt signals. If a parity error occurs on tag or data RAM during
AXI write transactions, a SLVERR response is reported back through a SLVERRINTR interrupt signal. For
Cortex-A9 Microprocessor Unit Subsystem
Send Feedback
on page 5-1
bit in the L2
Auxiliary Control register
Cache Maintenance Operations
L2_Cache_enable bit
register along with the corresponding interrupts in the general interrupt
L2 Cache Parity
.
registers.
of the L2
Control register
9-65
.
L2
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