Altera cyclone V Technical Reference page 801

Hard processor system

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staticcfg Fields

useeccasdata

This register controls the width of the physical DRAM interface.

Module Instance

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by

SDRAM Controller Subsystem

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Write with this bit set to apply all the settings loaded

in SDR registers to the memory interface. This bit is

write-only and always returns 0 if read.

This field allows the FPGA ports to directly access the

extra data bits that are normally used to hold the ECC

code. The interface width must be set to 24 or 40 in

This field specifies the DRAM burst length. The

following encodings set the burst length:

• 0x0= Burst length of 2 clocks

• 0x1= Burst length of 4 clocks

• 0x2= Burst length of 8 clocks

• 0x3= Burst length of 16 clocks

If you program the this field, you must also set the

membl field in the ctrlcfg register.

software or hardware. Any area of the memory map that is not explicitly defined as a register

space or accessible memory is considered reserved.

field in the

Base Address

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