Usb 2.0 Ulpi Phy Signal Description - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Additional connections on the USB OTG controller include:
• Clock input from the clock manager to the USB OTG controller
• Reset input from the reset manager to the USB OTG controller
• Interrupt line from the USB OTG controller to the microprocessor unit (MPU) global interrupt
controller (GIC).
The USB controller will only use Direct Shared IO 48.
Related Information
System Manager
•
Details available in the System Manager chapter.
General-Purpose I/O Interface
•

USB 2.0 ULPI PHY Signal Description

Table 18-1: ULPI PHY Interfaces
The ULPI PHY interface is synchronous to the
Port Name
ulpi_clk
ulpi_dir
ulpi_nxt
ulpi_stp
ulpi_data[7:0]
USB 2.0 OTG Controller
Send Feedback
on page 5-1
on page 22-1
Bit
Direction
Width
1 Input
1 Input
1 Input
1 Output
8 Bidirectional Bidirectional data bus. Driven low by the controller
USB 2.0 ULPI PHY Signal Description
signal coming from the PHY.
ulpi_clk
ULPI Clock
Receives the 60-MHz clock supplied by the
high-speed ULPI PHY. All signals are synchronous
to the positive edge of the clock.
ULPI Data Bus Control
1—The PHY has data to transfer to the USB OTG
controller.
0—The PHY does not have data to transfer.
ULPI Next Data Control
Indicates that the PHY has accepted the current byte
from the USB OTG controller. When the PHY is
transmitting, this signal indicates that a new byte is
available for the controller.
ULPI Stop Data Control
The controller drives this signal high to indicate the
end of its data stream. The controller can also drive
this signal high to request data from the PHY.
during idle.
Description
Altera Corporation
18-5