Altera cyclone V Technical Reference page 192

cv_5v4
2016.10.28
31 30
15 14
gpio_id add_ debou
encod nce
RO 0x0
ed_
param
0x0
s
RO
0x1
gpio_config_reg1 Fields
Bit
20:16
encoded_id_width
15
gpio_id
14
add_encoded_params
13
debounce
12
porta_intr
FPGA Manager
Send Feedback
29 28 27 26
Reserved
13 12 11 10
porta Reserved
_intr
RO RO
0x1
Name
This value is fixed at 32 bits.
Value
0x1f
Provides an ID code value
Value
0x0
Fixed to allow the indentification of the Designware
IP component.
Value
0x1
The value of this field is fixed to not allow debouncing
of the Port A signals.
Value
0x0
The value of this field is fixed to allow interrupts on
Port A.
Value
0x1
Bit Fields
25 24 23 22
9 8 7 6
hw_ portd portc
porta _ _
singl singl
RO
e_ctl e_ctl
0x0
RO RO
0x1 0x1
Description
Description
Width of ID Field
Description
GPIO ID Code Register Excluded
Description
Enable IP indentification
Description
Debounce is Disabled
Description
Port A Interrupts Enabled
gpio_config_reg1
21 20 19 18
encoded_id_width
RO 0x1F
5 4 3 2
portb porta num_ports
_ _
RO 0x0
singl singl
e_ctl e_ctl
RO RO
0x1 0x1
Access
4-49
17 16
1 0
apb_data_width
RO 0x2
Reset
RO 0x1F
RO 0x0
RO 0x1
RO 0x0
RO 0x1
Altera Corporation