Fpga Configuration - Altera cyclone V Technical Reference

4-4
Monitor
Monitor
The monitor block is an instance of the Synopsys DesignWareGPIO IP (DW_apb_gpio), which is a
separate instance of the IP that comprises the three HPS GPIO interfaces. The monitor block connects to
the configuration signals in the FPGA. This block monitors key signals related to FPGA configuration
such as
INIT_DON E
slave interface, and can either poll FPGA signals or be interrupted. The mon address map within the
FPGA manager register address map contains the monitor registers. For more information about FPGA
manager registers, refer to
You can program the FPGA manager to treat any of the monitor signals as interrupt sources. Independent
of the interrupt source type, the monitor block always drives an active-high level interrupt to the MPU.
Each interrupt source can be of the following types:
• Active-high level
• Active-low level
• Rising edge
• Falling edge

FPGA Configuration

You can configure the FPGA using an external device or through the HPS. This section highlights
configuring the FPGA through the HPS.
The FPGA CB uses the FPGA mode select (
The pins must be tied to the appropriate values for the configuration scheme. The table below lists
MSEL
supported
Altera Corporation
, , and
CRC_ERROR
FPGA Manager Address Map and Register Definitions
values when the FPGA is configured by the HPS.
MSEL
. Software configures the monitor block through the register
PR_DONE
) pins to determine which configuration scheme to use.
MSEL
cv_5v4
2016.10.28
on page 4-9
FPGA Manager
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