Local Memory Buffer - Altera cyclone V Technical Reference

18-10

Local Memory Buffer

• A soft reset must be issued before changing modes.
• If buffer DMA mode is selected, then the Host mode periodic request queue depth must not be set to
16.
• Devices must be re-enumerated.
Local Memory Buffer
The NAND flash controller has three local SRAM memory buffers.
• The write FIFO buffer is a 128 × 32-bit memory (512 total bytes)
• The read FIFO buffer is a 32 × 32-bit memory (128 total bytes)
• The ECC buffer is a 96 × 16-bit memory (1536 total bytes)
The SPRAM is a 8192 x 35-bit (32 data bits and 3 control bits) memory and includes support for ECC
(Error Checking and Correction). The ECC block is integrated around a memory wrapper. It provides
outputs to notify the system manager when single-bit correctable errors are detected (and corrected) and
when double-bit uncorrectable errors are detected. The ECC logic also allows the injection of single- and
double-bit errors for test purposes. The ECC feature is disabled by default. It must be initialized to enable
the ECC function.
Clocks
Table 18-2: USB OTG Controller Clock Inputs
All clocks must be operational when reset is released. No special handling is required on the clocks.
Clock Signal
usb_mp_clk
usb0_ulpi_clk
usb1_ulpi_clk
Resets
The USB OTG controller can be reset either through the hardware reset input or through software.
Reset Requirements
There must be a minimum of 12 cycles on the
During reset, the USB OTG controller asserts the
the
ulpi_stp
the
ulpi_stp
Software must ensure that the reset is active for a minimum of two
maximum assertion time.
Altera Corporation
Frequency
60 – 200 MHz Drives the master and slave interfaces, DMA controller, and
internal FIFO buffers
60 MHz ULPI reference clock for usb0 from external ULPI PHY I/O pin
60 MHz ULPI reference clock for usb1 from external ULPI PHY I/O pin
signal asserted. However, if the pin multiplexers are not programmed, the PHY does not see
signal. As a result, the
ulpi_clk
Functional Usage
clock before the controller is taken out of reset.
ulpi_clk
signal. The PHY outputs a clock when it sees
ulpi_stp
clock signal does not arrive at the USB OTG controller.
usb_mp_c lk
cv_5v4
2016.10.28
cycles. There is no
USB 2.0 OTG Controller
Send Feedback