Altera cyclone V Technical Reference page 616

8-34
Lightweight HPS-to-FPGA Bridge Master Signals
Signal
AWVALID
AWREADY
Table 8-11: Lightweight HPS-to-FPGA Bridge Master Write Data Channel Signals
Signal
WID
WDATA
WSTRB
WLAST
WVALID
WREADY
Table 8-12: Lightweight HPS-to-FPGA Bridge Master Write Response Channel Signals
Signal
BID
BRESP
BVALID
BREADY
Table 8-13: Lightweight HPS-to-FPGA Bridge Master Read Address Channel Signals
Signal
ARID
ARADDR
ARLEN
ARSIZE
ARBURST
Altera Corporation
Width Direction
1 bit Output
1 bit Input
Width Direction
12 bits Output
32 bits Output
4 bits Output
1 bit Output
1 bit Output
1 bit Input
Width Direction
12 bits Input
2 bits Input
1 bit Input
1 bit Output
Width Direction
12 bits Output
21 bits Output
4 bits Output
3 bits Output
2 bits Output
Description
Write address channel valid
Write address channel ready
Description
Write ID
Write data
Write data strobes
Write last data identifier
Write data channel valid
Write data channel ready
Description
Write response ID
Write response
Write response channel valid
Write response channel ready
Description
Read address ID
Read address
Burst length
Burst size
Burst type
cv_5v4
2016.10.28
HPS-FPGA Bridges
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