Flash-Related Special Function Operations - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
a.
pipe_cmd_err
b.
page_xfer_inc
c.
pipe_cpybck_cmd_comp
d.
load_comp
e.
ecc_uncor_error
f.
dma_cmd_comp
Timing Registers
You must optimize the following registers for your flash device's speed grade and clock frequency. The
NAND flash controller operates correctly with the power-on reset values. However, functioning with
power-on reset values is a non-optimal mode that provides loose timing (large margins to the signals).
Set the following registers in the
of the connected device and frequency of operation of the flash controller:
•
twhr2_and_we_2_re
•
tcwaw_and_addr_2_data
•
re_2_we
•
acc_clks
•
rdwr_en_lo_cnt
•
rdwr_en_hi_cnt
•
max_rd_delay
•
cs_setup_cnt
•
re_2_re
Registers to Ignore
You do not need to initialize the following registers in the
• The
transfer_spare_reg
• The
write_protect
feature.

Flash-Related Special Function Operations

This section describes all the special functions that can be performed on the flash memory.
The functions are defined by MAP10 commands as described in Command Mapping.
Related Information
Command Mapping
Erase Operations
Before data can be written to flash, an erase cycle must occur. The NAND flash memory controller
supports single block and multi-plane erases.
The controller decodes the block address from the indirect addressing shown in "MAP10 Command
Format".
Related Information
MAP10 Command Format
NAND Flash Controller
Send Feedback
(if the pipeline sequence is broken by a MAP01 command)
(at the end of each page data transfer)
(if failure)
(If DMA enabled)
group to optimize the NAND flash controller for the speed grade
config
register—Data transfer mode can be initialized using MAP10 commands.
register—Does not need initializing unless you are testing the write protection
on page 13-8
on page 13-11
Timing Registers
group:
config
13-25
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