Spi Legacy Mode - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
non-end-of-data writes to the flash memory only when the SRAM contains a full flash page of data, you
must set the watermark level to a value greater than one flash page to avoid the system stalling. You can
disable this watermark feature by writing a value of all ones to the
If the address of the write access is outside the range of the indirect trigger address, one of the following
actions occurs:
• When direct access mode is enabled, the write uses direct access mode.
• When direct access mode is disabled, the slave returns an error back to the requesting master.
You can cancel an indirect operation by setting the cancel indirect write bit (
to 1. For more information, refer to the "Indirect Write Operation with DMA Disabled" section.
Related Information
Indirect Write Operation with DMA Disabled
Consecutive Reads and Writes
It is possible to trigger two indirect operations at a time by triggering the
register twice in short succession. The second operation can be triggered while the first operation is in
progress. For example, software may trigger an indirect read or write operation while an indirect write
operation is in progress. The corresponding start and count registers must be configured properly before
software triggers each transfer operation.
This approach allows for a short turnaround time between the completion of one indirect operation and
the start of a second operation. Any attempt to queue more than two operations causes the indirect read
reject interrupt to be generated.

SPI Legacy Mode

SPI legacy mode allows software to access the internal TX FIFO and RX FIFO buffers directly, thus
bypassing the direct, indirect and STIG controllers. Software accesses the TX FIFO and RX FIFO buffers
by writing any value to any address through the data slave while legacy mode is enabled. You can enable
legacy mode with the legacy IP mode enable bit (
Legacy mode allows the user to issue any flash instruction to the flash device, but imposes a heavy software
overhead in order to manage the fill levels of the FIFO buffers effectively. The legacy SPI mode is bidirec‐
tional in nature, with data continuously being transferred both directions while the chip select is enabled.
If the driver only needs to read data from the flash device, dummy data must be written to ensure the chip
select stays active, and vice versa for write transactions.
For example, to perform a basic read of four bytes to a flash device that has three address bytes, software
must write a total of eight bytes to the TX FIFO buffer. The first byte would be the instruction opcode, the
next three bytes are the address, and the final four bytes would be dummy data to ensure the chip select
stays active while the read data is returned. Similarly, because eight bytes were written to the TX FIFO
buffer, software should expect eight bytes to be returned in the RX FIFO buffer. The first four bytes of this
would be discarded, leaving the final four bytes holding the data read from the device.
Because the TX FIFO and RX FIFO buffers are four bytes deep each, software must maintain the FIFO
buffer levels to ensure the TX FIFO buffer does not underflow and the RX FIFO buffer does not overflow.
Interrupts are provided to indicate when the fill levels pass the watermark levels, which are configurable
through the TX threshold register (
Quad SPI Flash Controller
Send Feedback
on page 15-16
enlegacyip
) and RX threshold register (
txtresh
Consecutive Reads and Writes
register.
indwrwater
) of the
cancel
bit of the
start
) of the register.
cfg
).
rxtresh
15-7
register
indwr
or
indrd indwr
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