Resets - Altera cyclone V Technical Reference

11-26

Resets

Clock Name
mpu_l2_ram_clk
l3_main_clk
f2h_sdram_clk[5:0]
In terms of clock relationships, the FPGA fabric connects the appropriate clocks to write data, read data,
and command ports for the constructed ports.
Related Information
Clock Manager
Resets
The SDRAM controller subsystem supports a full reset (cold reset) and a warm reset. The SDRAM
controller can be configured to preserve memory contents during a warm reset.
To preserve memory contents, the reset manager can request that the single-port controller place the
SDRAM in self-refresh mode prior to issuing the warm reset. If self-refresh mode is enabled before the
warm reset to preserve memory contents, the PHY and the memory timing logic is not reset, but the rest
of the controller is reset.
Related Information
Reset Manager
Taking the SDRAM Controller Subsystem Out of Reset
When a cold or warm reset is issued in the HPS, the Reset Manager resets this module and holds it in reset
until software releases it.
After the MPU boots up, it can deassert the reset signal by clearing the appropriate bits in the Reset
Manager's corresponding reset trigger.
Related Information
Modules Requiring Software Deassert
For more details about reset registers, refer to the Reset Manager.
Port Mappings
The memory interface controller has a set of command, read data, and write data ports that support AXI3,
AXI4 and Avalon-MM. Tables are provided to identify port assignments and functions.
Altera Corporation
Clock for MPU interface
Clock for L3 interface
Six separate clocks used for the FPGA-to-HPS SDRAM ports to the FPGA
fabric
on page 2-1
on page 3-1
on page 3-9
Description
SDRAM Controller Subsystem
cv_5v4
2016.10.28
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