Supported Phys - Altera cyclone V Technical Reference

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On the USB PHY layer, the USB OTG controller supports the following features:

• 8-bit ULPI PHY data width

• A single USB port connected to each OTG instance

• A ULPI connection to an off-chip USB transceiver

• Software-controlled access, supporting vendor-specific or optional PHY registers access to ease debug

• The OTG 2.0 support for Attach Detection Protocol (ADP) only through an external (off-chip) ADP

On the integration side, the USB OTG controller supports the following features:

• Different clocks for system and PHY interfaces

• Dedicated TX FIFO buffer for each device IN endpoint in direct memory access (DMA) mode

• Packet-based, dynamic FIFO memory allocation for endpoints for small FIFO buffers and flexible,

efficient use of RAM that can be dynamically sized by software

• Ability to change an endpoint's FIFO memory size during transfers

• Clock gating support during USB suspend and session-off modes

• PHY clock gating support

• System clock gating support

• Data FIFO RAM clock gating support

• Local buffering with error correction code (ECC) support

Note: The USB OTG controller does not support the following protocols:

• Enhanced Host Controller Interface (EHCI)

• Open Host Controller Interface (OHCI)

• Universal Host Controller Interface (UHCI)

Supported PHYS

The USB OTG controller only supports USB 2.0 ULPI PHYs. Only the single data rate (SDR) mode is

PHYs that support LPM mode may not function properly with the USB controller due to a timing issue. It

is recommended that designers use the MicroChip USB3300 PHY device that has been proven to be

successful on the development board.

Refer to the Cyclone V Device Datasheet for specific timing information.

USB 2.0 OTG Controller

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Supported PHYS

Altera Corporation

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