Altera cyclone V Technical Reference page 913

13-92
transfer_mode
err_block_addr2
Erred block address bank 2
intr_status3
Interrupt status register for bank 3
intr_en3
on page 13-111
Enables corresponding interrupt bit in interrupt register for bank 3
page_cnt3
Decrementing page count bank 3
err_page_addr3
Erred page address bank 3
err_block_addr3
Erred block address bank 3
transfer_mode
Current data transfer mode is Main only, Spare only or Main+Spare. This information is per bank.
Module Instance
nandregs
Offset:
0x400
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
transfer_mode Fields
Bit
7:6
value3
Altera Corporation
on page 13-108
on page 13-109
on page 13-112
on page 13-113
on page 13-114
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
[list][*]00 - Bank 3 is in Main mode [*]01 - Bank 3 is
in Spare mode [*]10 - Bank 3 is in Main+Spare
mode[/list]
Base Address
0xFFB80000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
value3
RO 0x0
Description
Register Address
0xFFB80400
21 20 19 18
5 4 3 2
value2 value1
RO 0x0 RO 0x0
Access
NAND Flash Controller
cv_5v4
2016.10.28
17 16
1 0
value0
RO 0x0
Reset
RO 0x0
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