Altera cyclone V Technical Reference page 362

5-168
GPLINMUX62
GPLINMUX61 Fields
Bit
0
sel
GPLINMUX62
Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects the input signal for GPIO/
LoanIO 62. Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified
after IO configuration.There is no support for dynamically changing the Pin Mux selections.
Module Instance
sysmgr
Offset:
0x5B0
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
GPLINMUX62 Fields
Bit
0
sel
GPLINMUX63
Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects the input signal for GPIO/
LoanIO 63. Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified
after IO configuration.There is no support for dynamically changing the Pin Mux selections.
Altera Corporation
Name
Select source for GPIO/LoanIO 61. 0 : Source for
GPIO/LoanIO 61 is GENERALIO13. 1 : Source for
GPIO/LoanIO 61 is MIXED2IO7.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
Select source for GPIO/LoanIO 62. 0 : Source for
GPIO/LoanIO 62 is GENERALIO14. 1 : Source for
GPIO/LoanIO 62 is GENERALIO23.
Description
Base Address
0xFFD08000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Access
Register Address
0xFFD085B0
21 20 19 18
5 4 3 2
Access
cv_5v4
2016.10.28
Reset
RW 0x0
17 16
1 0
sel
RW 0x0
Reset
RW 0x0
System Manager
Send Feedback