Reset Pins; Reset Effects; Altering Warm Reset System Response - Altera cyclone V Technical Reference

cv_5v4
2016.10.28

Reset Pins

Figure 3-5: Reset Pins
The test reset (
domain and are used to reset the TAP controller in the DAP. These pins are not connected to the reset
manager.
The and
nPOR
drain output as well. Any cold or warm reset drives the
manager pulls
register (
counts
connected to the HPS.

Reset Effects

The following list describes how reset affects HPS logic:
• The TAP reset domain ignores warm reset.
• The debug reset domain ignores warm reset.
• System reset domain cold resets ignore warm reset.
• Each module defines reset behavior individually.

Altering Warm Reset System Response

Registers in the clock manager, system manager, and reset manager control how warm reset affects the
HPS. You can control the impact of a warm reset on the clocks and I/O elements.
Altera strongly recommends using Altera-provided libraries to configure and control this functionality.
The default warm reset behavior takes all clocks and I/O elements through a cold reset response. As your
software becomes more stable or for debug purposes, you can alter the system response to a warm reset.
Reset Manager
Send Feedback
HPS
nTRST
TMS
TCK
nPOR
nRST
), test mode select (
nTRST
pins are used to request cold and warm resets respectively. The
nRST
low is controlled by the
nRST
). This technique can be used to reset external devices (such as external memories)
SoC Device
ARM DAP
Reset Manager
), and test clock ( ) pins are associated with the TAP reset
TMS TCK
pin low. The amount of time the reset
nRST
pin count field (
nRST
Reset Pins
pin is an open
nRST
) of the reset cycles count
nrstcnt
3-15
Altera Corporation