Altera cyclone V Technical Reference page 591

cv_5v4
2016.10.28
comp_id_2
Component ID2
comp_id_3
Component ID3
periph_id_4
JEP106 continuation code
Module Instance
fpga2hpsregs
Offset:
0x1FD0
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
periph_id_4 Fields
Bit
7:0
periph_id_4
periph_id_0
Peripheral ID0
Module Instance
fpga2hpsregs
Offset:
0x1FE0
Access:
RO
HPS-FPGA Bridges
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on page 8-13
on page 8-14
0xFF600000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
JEP106 continuation code
0xFF600000
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Base Address
periph_id_4
Register Address
0xFF601FD0
21 20 19 18
5 4 3 2
periph_id_4
RO 0x4
Access
Register Address
0xFF601FE0
8-9
17 16
1 0
Reset
RO 0x4
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