Altera cyclone V Technical Reference page 131

3-20
ctrl
software handshake. The software handshake sequence must match the hardware sequence. Software
mustde-assert the handshake request after asserting warm reset and before de-assert the warm reset. Fields
are only reset by a cold reset.
Module Instance
rstmgr
Offset:
0x4
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Reserved scanm scanm
grhsa grhsr
ck
RO
0x0
ctrl Fields
Bit
23
etrstallwarmrst
22
etrstallack
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
Reserved
13 12 11 10
scanm Reser fpgam
grhse ved grhsa
eq n ck
RW RW RO
0x0 0x0 0x0
Name
If a warm reset occurs and ETRSTALLEN is 1,
hardware sets this bit to 1 to indicate that the stall of
the ETR AXI master is pending. Hardware leaves the
ETR stalled until software clears this field by writing it
with 1. Software must only clear this field when it is
ready to have the ETR AXI master start making AXI
requests to write trace data.
This is the acknowlege for a ETR AXI master stall
initiated by the ETRSTALLREQ field. A 1 indicates
that the ETR has stalled its AXI master
Base Address
0xFFD05000
Bit Fields
25 24 23 22
etrst etrst
allwa allac
rmrst k
RW RO
0x0 0x0
9 8 7 6
fpgam fpgam Reser sdrse
grhsr grhse ved lfreq
eq n ack
RW RW RO
0x0 0x0 0x0
Description
Register Address
0xFFD05004
21 20 19 18
etrst etrst Reser fpgah
allre allen ved sack
q
RW RO
RW 0x1 0x0
0x0
5 4 3 2
sdrse sdrse Reserved
lfref lfref
req en
RW RW
0x0 0x0
cv_5v4
2016.10.28
17 16
fpgah fpgahsen
sreq
RW 0x0
RW
0x0
1 0
swwar swcoldr-
mrstr streq
eq
RW 0x0
RW
0x0
Access Reset
RW 0x0
RO 0x0
Reset Manager
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