Altera cyclone V Technical Reference page 56

cv_5v4
2016.10.28
Module Name
Interconnect
Boot ROM
On-chip RAM
Clock Manager
Send Feedback
System Clock Name
l3_main_clk
dbg_at_clk
dbg_clk
l3_mp_clk
l4_mp_clk
usb_mp_clk
nand_x_clk
cfg_clk
l3_sp_clk
l3_main_clk
mpu_l2_ram_clk
osc1_clk
spi_m_clk
l4_sp_clk
l4_mp_clk
l3_main_clk
l3_main_clk
Clock Usage By Module
Use
L3 main switch
System Trace Macrocell (STM)
slave and Embedded Trace
Router (ETR) master
connections
DAP master connection
L3 master peripheral switch
L4 MP bus, Secure Digital (SD) /
MultiMediaCard (MMC) master,
and EMAC masters
USB masters and slaves
NAND master
FPGA manager configuration
data slave
L3 slave peripheral switch
L4 SPIS bus master
ACP ID mapper slave and L2
master connections
L4 OSC1 bus master
L4 SPIM bus master
L4 SP bus master
Quad SPI bus slave
Boot ROM
On-chip RAM
Altera Corporation
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