Altera cyclone V Technical Reference page 68

cv_5v4
2016.10.28
intren Fields
Bit
5
sdrplllost
4
perplllost
3
mainplllost
2
sdrpllachieved
1
perpllachieved
0
mainpllachieved
dbctrl
Contains fields that control the debug clocks.
Module Instance
clkmgr
Offset:
0x10
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Clock Manager
Send Feedback
Name
When set to 1, the SDRAM PLL lost lock bit is ORed
into the Clock Manager interrupt output. When set to
0 the SDRAM PLL lost lock bit is not ORed into the
Clock Manager interrupt output.
When set to 1, the Peripheral PLL lost lock bit is
ORed into the Clock Manager interrupt output.
When set to 0 the Peripheral PLL lost lock bit is not
ORed into the Clock Manager interrupt output.
When set to 1, the Main PLL lost lock bit is ORed into
the Clock Manager interrupt output. When set to 0
the Main PLL lost lock bit is not ORed into the Clock
Manager interrupt output.
When set to 1, the SDRAM PLL achieved lock bit is
ORed into the Clock Manager interrupt output.
When set to 0 the SDRAM PLL achieved lock bit is
not ORed into the Clock Manager interrupt output.
When set to 1, the Peripheral PLL achieved lock bit is
ORed into the Clock Manager interrupt output.
When set to 0 the Peripheral PLL achieved lock bit is
not ORed into the Clock Manager interrupt output.
When set to 1, the Main PLL achieved lock bit is
ORed into the Clock Manager interrupt output.
When set to 0 the Main PLL achieved lock bit is not
ORed into the Clock Manager interrupt output.
0xFFD04000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Description
Base Address
2-31
dbctrl
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
Register Address
0xFFD04010
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