Altera cyclone V Technical Reference page 239

Hard processor system
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cv_5v4
2016.10.28
31
30
15
14
ctrl Fields
Bit
5
ptpclksel_1
4
ptpclksel_0
3:2
physel_1
System Manager
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29
28
27
26
13
12
11
10
Reserved
Name
Selects the source of the 1588 PTP reference clock.
This is sampled by an EMAC module when it exits
from reset. The field array index corresponds to the
EMAC index.
Value
0x0
0x1
Selects the source of the 1588 PTP reference clock.
This is sampled by an EMAC module when it exits
from reset. The field array index corresponds to the
EMAC index.
Value
0x0
0x1
Controls the PHY interface selection of the EMACs.
This is sampled by an EMAC module when it exits
from reset. The associated enum defines the allowed
values. The field array index corresponds to the
EMAC index.
Value
0x0
0x1
0x2
Bit Fields
25
24
23
22
Reserved
9
8
7
6
Description
Description
Selects osc1_clk
Selects fpga_ptp_ref_clk
Description
Selects osc1_clk
Selects fpga_ptp_ref_clk
Description
Select GMII/MII PHY interface
Select RGMII PHY interface
Select RMII PHY interface
21
20
19
18
5
4
3
2
ptpcl
ptpcl
physel_1
ksel_
ksel_
RW 0x2
1
0
RW
RW
0x0
0x0
Access
5-45
ctrl
17
16
1
0
physel_0
RW 0x2
Reset
RW
0x0
RW
0x0
RW
0x2
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