Altera cyclone V Technical Reference page 787

cv_5v4
2016.10.28
Bit
13:9
tcl
8:4
tal
3:0
tcwl
dramtiming2
This register implements JEDEC standardized timing parameters. It should be programmed in clock
cycles, for the value specified by the memory vendor.
Module Instance
sdr
Offset:
0x5008
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
Reserved
15 14
trcd
RW 0x0
dramtiming2 Fields
Bit
28:25
twtr
24:21
twr
20:17
trp
16:13
trcd
12:0
trefi
SDRAM Controller Subsystem
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Name
Memory read latency.
Memory additive latency.
Memory write latency.
0xFFC20000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
twtr
RW 0x0
13 12 11 10
Name
The write to read timing parameter.
The write recovery timing.
The precharge to activate timing parameter.
The activate to read/write timing parameter.
The refresh interval timing parameter.
Description
Base Address
Bit Fields
25 24 23 22
twr
RW 0x0
9 8 7 6
trefi
RW 0x0
Description
dramtiming2
Access
Register Address
0xFFC25008
21 20 19 18
trp
RW 0x0
5 4 3 2
Access
11-49
Reset
RW 0x0
RW 0x0
RW 0x0
17 16
trcd
RW 0x0
1 0
Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
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