Sd/Mmc Controller Signal Description - Altera cyclone V Technical Reference

14-4

SD/MMC Controller Signal Description

Figure 14-1: SD/MMC Controller Connectivity
L3
Interconnect
L
4
B
U
S
MPU
Subsystem
SD/MMC Controller Signal Description
The following table shows the SD/MMC controller signals that are routed to the FPGA and the HPS I/O.
Note: The last five signals in the table are not routed to HPS I/O, but only to the FPGA.
Table 14-3: SD/MMC Controller Interface I/O Pins
Signal
sdmmc_cclk_out
sdmmc_cmd_i
sdmmc_cmd_o
sdmmc_cmd_oe
sdmmc_pwr_ena_o
Altera Corporation
Bus Interface Unit
Master
DMA
Interface
Controller
Buffer
Control
Slave
Register
Interface
Block
Interrupt
Control
Width
1
1
1
1
SD/MMC Controller
FIFO
Synchronizer
Transmit/Receive
FIFO
ECC Interrupt
System
Manager
Direction
Out
In
Out
Out
Out
Card Interface Unit
Data Path
Control
FIFO
Command
Buffer
Path Control
Control
Clock
Control
Description
Clock from controller
to the card
Card command
External device power
enable
SD/MMC Controller
Send Feedback
cv_5v4
2016.10.28
I/O Pins
(Card Bus)