Ddr Calibration - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
To enable deep power down request for the LPDDR2 memories of one or both chip selects, program the
deeppwrdnreq
Other power-down modes are performed only under user control.
DDR PHY
The DDR PHY connects the memory controller and external memory devices in the speed critical
command path.
The DDR PHY implements the following functions:
• Calibration—the DDR PHY supports the JEDEC-specified steps to synchronize the memory timing
between the controller and the SDRAM chips. The calibration algorithm is implemented in software.
• Memory device initialization—the DDR PHY performs the mode register write operations to initialize
the devices. The DDR PHY handles re-initialization after a deep power down.
• Single-data-rate to double-data-rate conversion.

DDR Calibration

The SDRAM Controller calibrates across multiple SDRAM banks. An entire row is calibrated at bank 0
and bank 7 in each rank. Thus, if you have a 4 GB memory made up of two ranks, rank 0 is calibrated in
banks 0 and 7, and rank 1 is calibrated in banks 0 and 7.
You can refer to the "Interleaving Options" section to identify which memory locations are affected by
calibration.
Note: The SDRAM Controller does not preserve memory contents through a calibration cycle.
Related Information
Interleaving Options
Clocks
All clocks are assumed to be asynchronous with respect to the
transactions are synchronized to memory clock domain.
Table 11-11: SDRAM Controller Subsystem Clock Domains
Clock Name
ddr_dq_clk
ddr_dqs_clk
ddr_2x_dqs_clk
l4_sp_clk
SDRAM Controller Subsystem
Send Feedback
bit and the
deepwrdnmask
on page 11-17
Clock for PHY
Clock for MPFE, single-port controller, CSR access, and PHY
Clock for PHY that provides up to 2 times
Clock for CSR interface
field of the register.
lowpwreq
ddr_dqs_clk
Description
DDR PHY
memory clock. All
frequency
ddr_dq_clk
Altera Corporation
11-25