Document Revision History - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Register Group
DMA Channel
Thread Status
Reserved
AXI and Loop
Counter Status
Reserved
Debug
Reserved
Configuration
Reserved
Component ID

Document Revision History

Table 16-9: Document Revision History
Date
October 2016
DMA Controller
Send Feedback
Description
This address space is
allocated for the
registers that provide
the status of the DMA
channel threads.
This address space is
reserved.
This address space is
allocated for the
registers that provide
the AXI transfer status
and loop counter status
for each DMA channel
thread.
This address space is
reserved.
This address space is
allocated for the debug
registers.
This address space is
reserved.
This address space
holds registers that can
be read for
configuration data and
control watchdog
behavior.
This address space is
reserved.
This address space
holds peripheral ID
information.
Version
2016.10.28 Maintenance release
Start Address
0xFFE01100
0xFFE01140
0xFFE01400
0xFFE014F4
0xFFE01D00
0xFFE01D10
0xFFE01E00
0xFFE01E84
0xFFE01FE0
Changes
Document Revision History
End Address
0xFFE0113F
0xFFE013FF
0xFFE014F0
0xFFE01CFF
0xFFE01D0F
0xFFE01DFF
0xFFE01E80
0xFFE01FDF
0xFFE01FFF
Altera Corporation
16-63