Emac Initialization And Configuration - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
• Mixed Burst and AAL
• Fixed burst or undefined burst
• Burst length values and burst mode values
• Descriptor Length (only valid if Ring Mode is used)
5. Program the interface options in Register 10 (AXI Bus Mode Register). If fixed burst-length is enabled,
then select the maximum burst-length possible on the bus (bits[7:1]).
6. Create a proper descriptor chain for transmit and receive. In addition, ensure that the receive descrip‐
tors are owned by DMA (bit 31 of descriptor should be set). When OSF mode is used, at least two
descriptors are required.
7. Make sure that your software creates three or more different transmit or receive descriptors in the chain
before reusing any of the descriptors.
8. Initialize receive and transmit descriptor list address with the base address of the transmit and receive
descriptor (Register 3 (Receive Descriptor List Address Register) and Register 4 (Transmit Descriptor
List Address Register) respectively).
9. Program the following fields to initialize the mode of operation in Register 6 (Operation Mode
Register):
• Receive and Transmit Store And Forward
• Receive and Transmit Threshold Control (RTC and TTC)
• Hardware Flow Control enable
• Flow Control Activation and De-activation thresholds for MTL Receive and Transmit FIFO buffers
(RFA and RFD)
• Error frame and undersized good frame forwarding enable
• OSF Mode
10.Clear the interrupt requests, by writing to those bits of the status register (interrupt bits only) that are
set. For example, by writing 1 into bit 16, the normal interrupt summary clears this bit (DMA Register
5 (Status Register)).
11.Enable the interrupts by programming Register 7 (Interrupt Enable Register).
Note: Perform step
12.Read Register 11 (AHB or AXI Status) to confirm that all previous transactions are complete.
Note: If any previous transaction is still in progress when you read the Register 11 (AXI Status), then it
is strongly recommended to check the slave components addressed by the master interface.
13.Start the receive and transmit DMA by setting SR (bit 1) and ST (bit 13) of the control register (DMA
Register 6 (Operation Mode Register).

EMAC Initialization and Configuration

The following EMAC configuration operations can be performed after DMA initialization. If the EMAC
initialization and configuration is done before the DMA is set up, then enable the MAC receiver (last step
below) only after the DMA is active. Otherwise, the received frame could fill the RX FIFO buffer and
overflow.
1. Program the
external PHY. Bits[15:11] of the
(61) The Cyclone V implementation supports bits [3:1].
Ethernet Media Access Controller
Send Feedback
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on page 1-67 only if you did not perform step
GMII Address Register
GMII Address Register
EMAC Initialization and Configuration
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(offset 0x10) for controlling the management cycles for the
are written with the Physical Layer Address
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(61)
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on page 1-66.
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Altera Corporation
17-67
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