Altera cyclone V Technical Reference page 270

5-76
usb0
31 30
15 14
ocram Fields
Bit
4
derr
3
serr
2
injd
1
injs
0
en
usb0
This register is used to enable ECC on the USB0 RAM. ECC errors can be injected into the write path
using bits in this register. This register contains interrupt status of the ECC single/double bit error. Only
reset by a cold reset (ignores warm reset).
Module Instance
sysmgr
Offset:
0x148
Access:
RW
Altera Corporation
29 28 27 26
13 12 11 10
Reserved
Name
This bit is an interrupt status bit for On-chip RAM
ECC double bit, non-correctable error. It is set by
hardware when double bit, non-correctable error
occurs in On-chip RAM. Software needs to write 1
into this bit to clear the interrupt status.
This bit is an interrupt status bit for On-chip RAM
ECC single, correctable error. It is set by hardware
when single, correctable error occurs in On-chip
RAM. Software needs to write 1 into this bit to clear
the interrupt status.
Changing this bit from zero to one injects a double,
non-correctable error into the On-chip RAM. This
only injects one double bit error into the On-chip
RAM.
Changing this bit from zero to one injects a single,
correctable error into the On-chip RAM. This only
injects one error into the On-chip RAM.
Enable ECC for On-chip RAM
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Base Address
0xFFD08000
21 20 19 18
5 4 3 2
derr serr injd
RW RW RW
0x0 0x0 0x0
Access
Register Address
0xFFD08148
cv_5v4
2016.10.28
17 16
1 0
injs en
RW RW 0x0
0x0
Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
System Manager
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