Altera cyclone V Technical Reference page 277

cv_5v4
2016.10.28
Bit
0
en
can0
This register is used to enable ECC on the CAN0 RAM. ECC errors can be injected into the write path
using bits in this register. This register contains interrupt status of the ECC single/double bit error. Only
reset by a cold reset (ignores warm reset).
Module Instance
sysmgr
Offset:
0x15C
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
can0 Fields
Bit
4
derr
3
serr
System Manager
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Name
Enable ECC for DMA RAM
0xFFD08000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
This bit is an interrupt status bit for CAN0 RAM ECC
double bit, non-correctable error. It is set by hardware
when double bit, non-correctable error occurs in
CAN0 RAM. Software needs to write 1 into this bit to
clear the interrupt status.
This bit is an interrupt status bit for CAN0 RAM ECC
single, correctable error. It is set by hardware when
single, correctable error occurs in CAN0 RAM.
Software needs to write 1 into this bit to clear the
interrupt status.
Description
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Access
Register Address
0xFFD0815C
21 20 19 18
5 4 3 2
derr serr injd
RW RW RW
0x0 0x0 0x0
Access
5-83
can0
Reset
RW 0x0
17 16
1 0
injs en
RW RW 0x0
0x0
Reset
RW 0x0
RW 0x0
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