Altera cyclone V Technical Reference page 698

9-62
Implementation Details
• Two master ports connected to the following slave ports:
• SDRAM controller, 64-bit slave port width
• L3 interconnect, 64-bit slave port width
• Cache lockdown capabilities as follows:
• Line lockdown
• Lockdown by way
• Lockdown by master (both processors and ACP masters)
• TrustZone support
• Cache event monitoring
Related Information
L2 Cache Event Monitoring
•
• System Manager
For more information about SEU errors, refer to the System Manager chapter.
• ARM Infocenter
For more information about AXI user sideband signals, refer to the CoreLink Level 2 Cache Controller
L2C-310 Technical Reference Manual, which you can download from the ARM Infocenter website.
Implementation Details
The following table shows the parameter settings for the cache controller.
Table 9-10: Cache Controller Configuration
Cache way size
Number of cache ways
Tag RAM write latency
Tag RAM read latency
Tag RAM setup latency
Data RAM write latency
Data RAM read latency
Data RAM setup latency
Parity logic
Lockdown by master
Lockdown by line
Altera Corporation
on page 9-63
on page 5-1
Feature Meaning
64 KB
8 ways
1
1
1
1
2
1
Parity logic enabled
Lockdown by master enabled
Lockdown by line enabled
Cortex-A9 Microprocessor Unit Subsystem
cv_5v4
2016.10.28
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