Altera cyclone V Technical Reference page 240

5-46
l3master
Bit
1:0
physel_0
l3master
Controls the L3 master ARCACHE and AWCACHE AXI signals. These register bits should be updated
only during system initialization prior to removing the peripheral from reset. They may not be changed
dynamically during peripheral operation All fields are reset by a cold or warm reset.
Module Instance
sysmgr
Offset:
0x64
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
awcache_1
RW 0x0
Altera Corporation
Name
Controls the PHY interface selection of the EMACs.
This is sampled by an EMAC module when it exits
from reset. The associated enum defines the allowed
values. The field array index corresponds to the
EMAC index.
Value
0x0
0x1
0x2
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
awcache_0
RW 0x0
Description
Description
Select GMII/MII PHY interface
Select RGMII PHY interface
Select RMII PHY interface
Base Address
0xFFD08000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
arcache_1
RW 0x0
Access
Register Address
0xFFD08064
21 20 19 18
5 4 3 2
arcache_0
cv_5v4
2016.10.28
Reset
RW 0x2
17 16
1 0
RW 0x0
System Manager
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