Altera cyclone V Technical Reference page 627

cv_5v4
2016.10.28
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
ahb_cntl Fields
Bit
1
force_incr
0
decerr_en
HPS2FPGA AXI Bridge Registers Register Descriptions
Registers associated with the HPS2FPGA master interface. This master interface provides access to the
registers in the HPS2FPGA AXI Bridge.
Offset:
0x1000
fn_mod_bm_iss
Sets the issuing capability of the preceding switch arbitration scheme to multiple or single outstanding
transactions.
ahb_cntl
on page 8-46
Sets the block issuing capability to one outstanding transaction.
HPS-FPGA Bridges
Send Feedback
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
Value
0x0
0x1
Value
0x0
0x1
on page 8-46
HPS2FPGA AXI Bridge Registers Register Descriptions
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Description
Multiple outstanding write transactions
If a beat is received that has no write data
strobes set, that write data beat is replaced
with an IDLE beat. Also, causes all transac‐
tions that are to be output to the AHB
domain to be an undefined length INCR.
Description
No DECERR response.
If the AHB protocol conversion function
receives an unaligned address or a write data
beat without all the byte strobes set, creates a
DECERR response.
21 20 19 18
5 4 3 2
Access
RW
RW
8-45
17 16
1 0
force decerr_
_incr en
RW RW 0x0
0x0
Reset
0x0
0x0
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