Altera cyclone V Technical Reference page 561

cv_5v4
2016.10.28
read_qos
on page 7-113
QoS (Quality of Service) value for the read channel.
write_qos
QoS (Quality of Service) value for the write channel.
fn_mod
on page 7-115
Sets the block issuing capability to multiple or single outstanding transactions.
wr_tidemark
Controls the release of the transaction in the write data FIFO.
Module Instance
l3regs
Offset:
0x46040
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
wr_tidemark Fields
Bit
3:0
level
read_qos
QoS (Quality of Service) value for the read channel.
Module Instance
l3regs
System Interconnect
Send Feedback
on page 7-114
0xFF800000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
Stalls the transaction in the write data FIFO until the
number of occupied slots in the write data FIFO
exceeds the level. Note that the transaction is released
before this level is achieved if the network receives the
WLAST beat or the write FIFO becomes full.
0xFF800000
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Base Address
wr_tidemark
Register Address
0xFF846040
21 20 19 18
5 4 3 2
RW 0x4
Access
Register Address
0xFF846100
7-113
17 16
1 0
level
Reset
RW 0x4
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