Descriptor Overview - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
DMA controller can resume operation only after soft resetting or hard resetting the EMAC and reinitial‐
izing the DMA.

Descriptor Overview

The DMA in the Ethernet subsystem transfers data based on a single enhanced descriptor, as explained in
the DMA Controller section. The enhanced descriptor is created in the system memory. The descriptor
addresses must be word-aligned.
The enhanced or alternate descriptor format can have 8 DWORDS (32 bytes) instead of 4 DWORDS as in
the case of the normal descriptor format.
The features of the enhanced or alternate descriptor structure are:
• The alternative descriptor structure is implemented to support buffers of up to 8 KB (useful for Jumbo
frames).
• There is a re-assignment of control and status bits in TDES0, TDES1, RDES0 (advanced timestamp or
IPC full offload configuration)​, and RDES1.
• The transmit descriptor stores the timestamp in TDES6 and TDES7 when you select the advanced
timestamp.
• The receive descriptor structure is also used for storing the extended status (RDES4) and timestamp
(RDES6 and RDES7) when advanced timestamp, IPC Full Checksum Offload Engine, or Layer 3 and
Layer 4 filter feature is selected.
• You can select one of the following options for descriptor structure:
• If timestamping is enabled in Register 448 (Timestamp Control Register) or Checksum Offload is
enabled in Register 0 (MAC Configuration Register), the software must to allocate 32 bytes (8
DWORDS) of memory for every descriptor by setting Bit 7 (Descriptor Size) of Register 0 (Bus
Mode Register).
• If timestamping or Checksum Offload is not enabled, the extended descriptors (DES4 to DES7) are
not required. Therefore, software can use descriptors with the default size of 16 bytes (4 DWORDS)
by clearing Bit 7 (Descriptor Size) of Register 0 (Bus Mode Register) to 0.
Related Information
DMA Controller
Transmit Descriptor
The application software must program the control bits TDES0[31:18] during the transmit descriptor
initialization. When the DMA updates the descriptor, it writes back all the control bits except the OWN bit
(which it clears) and updates the status bits[7:0].
With the advance timestamp support, the snapshot of the timestamp to be taken can be enabled for a
given frame by setting Bit 25 (TTSE) of TDES0. When the descriptor is closed (that is, when the OWN bit
is cleared), the timestamp is written into TDES6 and TDES7 as indicated by the status Bit 17 (TTSS) of
TDES0.
Note: Only enhanced descriptor formats (4 or 8 DWORDS) are supported.
Note: When the advanced timestamp feature is enabled, software should set Bit 7 of Register 0 (Bus Mode
Register), so that the DMA operates with extended descriptor size. When this control bit is clear,
the TDES4-TDES7 descriptor space is not valid.
Ethernet Media Access Controller
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Descriptor Overview
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