Writing A Predefined Data Pattern To Sdram In The Preloader - Altera cyclone V Technical Reference

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Writing a Predefined Data Pattern to SDRAM in the Preloader

Writing a Predefined Data Pattern to SDRAM in the Preloader
You can include your own code to write a predefined data pattern to the SDRAM in the preloader for
debugging purposes.
1. Include your code in the file:
arm\cpu\armv7\socfpga\spl.c
Adding the following code to the
repeated five times, to the SDRAM.
/*added for demo, place after the last #define statement in spl.c */
#define ROTATE_RIGHT(X) ( (X>>1) | (X&1?0X80000000:0) )
/*added for demo, place after the calibration code */
test_data_walk0((long *)0x100000,PHYS_SDRAM_1_SIZE);
int test_data_walk0(long *base, long maxsize)
{
volatile long *addr;
long
ulong
ulong
printf("\nSTARTED %08X DATA PATTERN !!!!\n",data_temp[i]);
/*write*/
for (cnt = (0+i*num_address); cnt < ((i+1)*num_address) ;
/*read*/
for (cnt = (0+i*num_address); cnt < ((i+1)*num_address) ; cnt = cnt++ ) {
expected_data[i],read_data);
}
}
}
====//End Of Code//=====
Altera Corporation
<project_folder>\software\spl_bsp\uboot-socfpga\arch\
spl.c
cnt;
data_temp[3];
ulong expected_data[3];
read_data;
int i = 0;
int num_address;
num_address=50;
data_temp[0]=0XFFFFFFFE; //initial data for walking 0 pattern
data_temp[1]=0X00000001; //initial data for walking 1 pattern
data_temp[2]=0XAAAAAAAA; //initial data for A->5 switching
expected_data[0]=0XFFFFFFFE; //initial data for walking 0 pattern
expected_data[1]=0X00000001; //initial data for walking 1 pattern
expected_data[2]=0XAAAAAAAA; //initial data for A->5 switching
for (i=0;i<3;i++) {
addr = base + cnt;
sync ();
*addr = data_temp[i];
data_temp[i]=ROTATE_RIGHT(data_temp[i]);
}
addr = base + cnt;
sync ();
read_data=*addr;
printf("Address:%X
if (expected_data[i] !=read_data) {
puts("!!!!!!FAILED!!!!!!\n\n");
hang();
}
expected_data[i]=ROTATE_RIGHT(expected_data[i]);
.
file causes the controller to write walking 1s and walking 0s,
//counter to loop different data pattern
/* pointer arith! */
/* pointer arith! */
Expected: %08X
cnt++ ) {
Read:%08X \n",addr,
SDRAM Controller Subsystem
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cv_5v4
2016.10.28